1. Field of the Invention
The present invention relates to a wiring board where on electronic components such as LSI chips are mounted on the surface thereof and, more particularly, to a low-impedance wiring board having an electric element such as a capacitor incorporated in the wiring board.
2. Description of Related Art
Recently, as telecommunication apparatuses proliferate, electronic equipment operating at a high speed is increasingly used and accordingly demands for electronic packages capable of operating at high speeds are increasing. In order for a high speed operation, noises on electric signals must be minimized. This requires that passive electronic components such as capacitors be placed in proximity to active electronic components and that the wiring length of electronic circuits be minimized, thereby to reduce the inductance of the interconnection lines.
For example, Japanese Unexamined Patent Publication (Kokai) No. 7-142871 (1995) proposes that a bypass capacitor is formed between a planar pattern drawn from a power supply layer and a planar pattern drawn from ground layer. In this constitution, however, electromagnetic field concentrates in a small number of via hole conductors that are connected to a power supply layer formed inside of the wiring board or the planar electrode used to lead from the ground layer. There is also such a problem that increasing the number of the via hole conductors used in interconnection leads to a decrease in the capacity of the dielectric layer.
Japanese Unexamined Patent Publication (Kokai) No. 10-92966 (1998) proposes that a chip capacitor is mounted near a cavity wherein a semiconductor device is hermetically sealed, whereby the chip capacitor is disposed as near to the semiconductor device as possible. However, since the capacitor is mounted in portions different from the portion where the semiconductor device is wired, wiring length increases, resulting in increasing value of inductance. That is, connection between the capacitor and the semiconductor device requires it to make wiring through the via hole conductors and the wiring circuit formed in the dielectric substrate.
In Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999), such a wiring board is proposed as all insulation layers that constitute a dielectric substrate are formed from a mixture including an inorganic filler and a thermosetting resin, in relation to a module incorporating circuit components and a method of producing the same. However, this circuit board has such a problem as the weak mechanical strength and low rigidity of the board cause the wiring board to deform with a flip chip portion warping, when the semiconductor device is mounted on the surface of the wiring board by flip chip mounting procedure.
Moreover, for example, Japanese Unexamined Patent Publication (Kokai) No. 2-121393 (1990) proposes to embed a chip capacitor in an insulation layer between a power supply layer and a ground layer. In Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999) and Japanese Unexamined Patent Publication (Kokai) No. 10-51150 (1998) such wiring boards are proposed as semiconductor devices and capacitors are incorporated in a dielectric substrate.
In the constitution disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2-121393 (1990), ceramic chip capacitors embedded in an insulation layer between a power supply layer pattern and a ground layer pattern are supported by the surrounding insulation layers. However, connections between the terminal electrodes of the capacitor, power supply layer in the substrate and the ground layer are made by pressure contact. As a result, when subjected to a thermal shock, the connection performance between the terminal electrode and the wiring circuit layer changes due to the difference in the thermal expansion coefficient.
Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999) also proposes to connect the electrodes of a semiconductor device and a wiring circuit layer by means of a conductor such as gold, silver, copper, nickel or solder. However, in the case that an electronic component such as semiconductor device is soldered onto the surface of a wiring board, there has been such a problem that the connection performance between the terminal electrode and the wiring circuit layer changes when the solder is reflowed at a temperature from 220 to 300xc2x0 C. Where the component incorporated inside is a capacitor, in particular, inductance due to the capacitor increases, thus leading to a change or deterioration of the function of the capacitor to remove noise.
Moreover, in the capacitor incorporating wiring board of the prior art described in for example, Japanese Unexamined Patent Publication (Kokai) No. 2-121393 (1990), Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999) or Japanese Unexamined Patent Publication (Kokai) No. 10-51150 (1998), there is a problem of low reliability of connection between the capacitor and the wiring circuit layer on the wiring board when thermal cycles or stress is exerted thereon.
Such a method has been proposed for fastening a capacitor on a wiring board that a clearance between the capacitor and an insulation layer is filled with a thermosetting resin and the thermosetting resin is hardened together with the insulation layer thereby to bond firmly.
However, since the capacitor has lower thermal expansion coefficient than the insulation layer, the capacitor is subjected to stress when thermal cycles are applied. The stress may damage the capacitor or impair the reliability of the connection thereof with the wiring circuit layer.
In the case of for example, Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999), although a constitution of incorporating semiconductor device and/or chip electric components in a wiring board is described, there is no description on a relation with via hole conductors of the wiring board or the conductor layer where an electric circuit is to be formed, or on the relation between the via hole conductors connected to a plurality of electric components. For example, in the case that via holes where currents flow in the same direction are located close to each other, the effect of the mutual inductance of the two via hole conductors becomes conspicuous particularly when a signal of high frequency is transmitted, resulting in an increase in the inductance of the wiring.
A first object of the present invention is to provide a constitution of a wiring board that reduces the generation of noise due to high speed operation of electronic components and effectively decreases the inductance due to electric elements disposed near an electronic components.
A second object of the present invention is to provide a wiring board that incorporates electric elements such as capacitors inside a dielectric substrate thereof, and ensures excellent performance and reliability of mounting components even in the case of flip-chip mounting of electronic components such as semiconductor devices on the surface of the substrate.
A third object of the present invention is to provide an electric element incorporating wiring board having excellent reliability of connection between electric elements incorporated inside thereof and a wiring circuit layer formed on the wiring board.
A fourth object of the present invention is to provide an electric element incorporating wiring board that incorporates electric elements such as capacitors inside a dielectric substrate thereof, and maintains connection between the electric elements incorporated inside thereof and a wiring circuit layer formed on the wiring board with such an excellent reliability that the functions of the incorporated electric elements does not change after reflow of solder for mounting electronic components on the surface.
The present inventors have intensively studied about the electric element incorporating wiring board that incorporates electric elements inside an dielectric substrate thereof, and has electronic components mounting surface on the dielectric substrate, for achieving the objects described above. Consequently, the present inventors arrived at such a constitution as an electric element having at least two first terminal electrodes and at least two second terminal electrodes is used as an electric element incorporated in a dielectric substrate, a first and a second electrically conductive layer are formed inside of the dielectric substrate disposed between the electric element and the surface of the dielectric substrate, all of the first terminal electrodes of the electric element are connected to the first conductive layer and all of the second terminal electrodes of the electric element are connected to the second conductive layer, while via hole conductors that penetrate through the first and the second conductive layers are formed to reach the surface of the dielectric substrate, and the via hole conductors and an electronic component such as semiconductor device mounted on the board surface are electrically connected to each other.
Thickness of the insulation layer disposed between the conductive layer and the dielectric substrate surface is preferably 0.3 mm or less.
In case a capacitor having two or more positive terminal electrodes and two or more negative terminal electrodes is used as the electric element, for example, the capacitor itself has a low inductance. When connecting the low-inductance capacitor and the electronic component, the positive terminal electrodes and the negative terminal electrodes of the capacitor are each connected to one of the conductive layers, while the conductive layer and the electronic component are connected through the via hole conductors. Since the distance between the conductive layer and the electronic component can be decreased by decreasing the thickness of the insulation layer disposed between the conductive layer and the board surface, the inductance can be effectively reduced.
The dielectric substrate is preferably made in a laminated structure comprising a first insulation layer made of a mixture of a thermosetting resin and an inorganic filler and a second insulation layer made of a fibrous material impregnated with a thermosetting resin. In this case, it is preferable that the electric element is incorporated in the first insulation layer and the difference in the thermal expansion coefficient between the electric element and the first insulation layer is 7xc3x9710xe2x88x926/xc2x0 C. or less. It is also preferable that the second insulation layer is located at the top surface of the dielectric substrate.
Thermal expansion coefficient of the first insulation layer made of the mixture of the thermosetting resin and the inorganic filler can be easily altered by properly selecting the type and quantity of the filler. Thus the thermal expansion coefficient of the first insulation layer can be easily matched to that of the electric element to be embedded in the first insulation layer. Thus it is made possible to suppress the stress caused by the difference in the thermal expansion coefficient, and thereby minimizing the deformation of the wiring board and improve the reliability of connection between the wiring circuit layer of the wiring board and the electric element.
On the other hand, when the dielectric substrate is made of only the first insulation layer made of the mixture of the thermosetting resin and the inorganic filler, the substrate has a lower strength as a whole and the surface flatness is likely to be impaired. Therefore the second insulation layer made of the fibrous material impregnated with the thermosetting resin is stacked on the top or bottom surface of the insulation layer made of the mixture of the thermosetting resin and the inorganic filler. This increases the strength of the first insulation layer and, at the same time, improves the flatness of the wiring board surface, thereby achieving the wiring board that can be used satisfactorily even when semiconductor devices are mounted by flip chip bonding.
It is also preferable that terminal electrodes of the electric element and the via hole conductors are directly connected to each other, and the junctions between the terminal electrodes and the via hole conductors include an intermetallic compound of Cu and Sn. In this case, the via hole conductor preferably includes Cu and Sn as metallic components. Proportion of Sn to the total metal component (Cu+Sn) by weight is preferably in a range from 0.5 to 0.95. Further, an electrically conductive layer including at least Sn is preferably formed on the top surface of the terminal electrodes of the electric element.
Specifically, a Sn-containing conductive layer is formed on the top surface of the terminal electrodes of the electric element, and the via hole conductors are caused to contain Cu and Sn, and the board is heated to a temperature of 210xc2x0 C. or higher. This causes the metallic component based on Cu and Sn included in the via hole conductors and the Sn component of the terminal of the electric element to react with each other, so that intermetallic compounds of Cu and Sn such as Cu3Sn or Cu6Sn5 that are excellent in the electrical conductivity and in heat resistance are formed, in addition to Cu and Sn, in the junctions between the via hole conductors and the terminal electrodes of the electric element. As a result, electrical connection between the via hole conductors and the terminal of the electric element can be improved. Consequently, even when subjected to sudden heating from the outside due to solder reflow or the like, the connection performance between the terminal electrodes and the via hole conductors does not change. Thus it is made possible to prevent the inductance of the electric element from increasing and achieve stable function.
Reliability of connection can be improved further by making the area of the connecting surface of the terminals of the electric elements with the via hole conductors larger than the sectional area of the via hole conductor.
In the electric element incorporating wiring board described above, the capacitor used as the electrical element can be caused to function as a decoupling capacitor. Thus switching noise generated in the operation of the semiconductor device mounted on the wiring board can be effectively reduced.
A plurality of capacitors can be incorporated in the electric element incorporating wiring board. In this case, it is preferable to incorporate capacitors of different values of capacitance. This makes it possible for the plurality of capacitors having different resonant frequencies to function in an integrated form, and results in the capability to achieve low impedance in a wider range and keep the inductance lower over wider frequency band.
In case a plurality of electric elements are incorporated in the dielectric substrate, it is preferable to connect a pair of via hole conductors, that are most proximate to each other between adjacent electric elements, to different conductive layers among the first and second conductive layers, so that currents flow in different directions in the via hole conductors. Since the mutual inductance of the interconnection including the via hole conductors can be decreased in this configuration, the electric elements can be mounted with a higher density. A wiring board having a low inductance can be achieved even when the space between a pair of via hole conductors that are most proximate to each other between adjacent electric elements is set to 0.5 mm or less.
The surface of the electric element other than the first and second terminal electrodes is preferably covered by a thermoplastic resin that has glass transition point not higher than 100xc2x0 C. This makes it possible to maintain high reliability of connection between the electric elements and the wiring layer even when the wiring board is subjected to thermal shock due to thermal cycles or solder reflow.
The above objects and other objects, features and effects of the present invention will become more apparent by the description of preferred embodiments that follows with reference to the accompanying drawings.